Sunday, 4 May 2014

Timex contended memory timings, the TS2068 kludge board and EXROM at $4000 - $7FFF

This was first posted on the World of Spectrum hardware forum.

I haven't seen this documented anywhere yet so I thought I'd share my findings. I've been investigating contended memory timings on the Timex Sinclair 2068, in particular what happens when you page in EXROM or cartridge memory in $4000 - $7FFF.

It appears the Timex SCLD still applies memory contention at these locations when the RAM is paged out. I've written a short program which plays beeps using a machine code routine which steps through $4000 - $7FFF making a memory access at each location during the beep timing loop.

When this program runs it plays the same modulated tone regardless of the setting of port F4 bits 2 and 3. When the program steps through $0000 - $3FFF or $8000 - $FFFF you get a higher, pure tone also regardless of the setting of port F4 bits 0 and 1 or 4 - 7.

So the Timex SCLD pays no attention to bits 2 and 3 in port F4 when applying memory contention; contention is applied whether the CPU is accessing contended video memory or "uncontended" ROM in the EXROM socket or the cartridge port. So we might as well call this "contended ROM".

This solves one other small mystery - the kludge board in every TS2068. Like the dead cockroach it consists of a 74LS00 quad 2-input NAND gate chip; however it is not there to fix I/O contention.

Timex SCLDs can be thought of as a modification of 5C112E ULAs. They have the fixed I/O contention of the 5C112E and the same sync pulse and colour burst timing. You get a nice, centred picture, at the expense of the display not working on some televisions because the colour burst comes too late.

The problem with the SCLD seems to be the tristate signal (TS#) which is used to put the Z80 multiplexed address bus and data bus onto the SCLD/VRAM buses. This signal should go low during memory accesses to $4000 - $7FFF but only when (HOME) RAM is enabled at those locations.

From the design of the kludge circuit it seems that TS# coming from the SCLD goes low at those addresses whether the RAM is switched in or not. The kludge circuit fixes this for the cartridge port and the Bus Expansion unit (BE# signal on the edge connector) but not for the EXROM. Otherwise the CPU would read or write to the VRAM at those addresses as well as the cartridge memory or bus expansion device. For reads there would be a conflict on the bus with two devices trying to assert the bus; for writes both devices would receive the written value.

Curiously the kludge circuit does not fix the problem for the EXROM. Presumably this was because the Timex engineers felt that no-one would ever page EXROM in at $4000 - $7FFF, or at least not usefully. The EXROM chip in the standard machine is only 8K long and is written for $0000-$1FFF. If the EXROM is selected at $4000-$7FFF, it will conflict with the VRAM at the same locations when those locations are read.

The Timex Sinclair 2068 cannot reliably access EXROM between $4000 - $7FFF.


I need to do a little more investigating, this time with an oscilloscope. I'm pretty sure TS# is low during memory accesses to $4000 - $7FFF with EXROM paged in, but I'm not sure what happens to the VRAM signals RAS1# and CAS1#.

Second update:

I did an investigation using an oscilloscope today. Results will be explained in a follow up post.

No comments: